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Үйлдлийн өсгөгч нь хамгийн зайлшгүй шаардлагатай электрон төхөөрөмж гэж тооцогддог. Энэхүү өгүүлэл нь хоёр шатлалт CMOS үйлдлийн өсгөгч (ҮӨ) зохион бүтээх, ҮӨ дизайны шинж чанарт янз бүрийн параметрүүдийн нөлөөллийг шинжилсэн бөгөөд ҮӨ -ийн өсгөлтийн дизайн дээр голчлон анхаарсан. Үүнийг гол зүйл болгон хадгалахын тулд ҮӨ -ийн өсгөлт(gain), фазын маржин(phase margin), өөрчлөлтийн хурд(slew rate), чадлын зарцуулалт(power dissipation) болон бусад үзүүлэлтүүдийг авч үздэг. Энэхүү ажил нь 1.5V тэжээлийн хүчдэлд ажилладаг хоёр үе шатлалт CMOS үйлдлийн өсгөгчийн дизайн, хэрэгжилтийг танилцуулж байгаа бөгөөд Симуляцийн процессыг 90нм технологи бүхий Cadence Virtuoso ашиглан гүйцэтгэсэн. Гаргасан дизайны параметрүүд нь фазын маржин-55.4°, өсгөлт-76,16дБ, чадлын зарцуулалт 0,19 мВт байна.
Abstract—CRYSTALS-Kyber is a new algorithm that the NIST recently selected to standardize public-key encryption and key establishment. Therefore, studies are needed to evaluate the sidechannel attack resistance of CRYSTALS-Kyber mplementations. This paper presents a simple power analysis of a CRYSTALSKyber hardware implementation with the security parameter k=3. Since hardware implementations perform computations in parallel, the power consumption of each operation is difficult to quantify. The entire power consumption trace was identified using 6,072,500 samples during the CCAKEM implementation of Kyber. A significant part of the message encoding power consumption occurred during decapsulation. These findings show that existing hardware implementations of CRYSTALS-Kyber require effective countermeasures to efficiently resist side-channel attacks.
An ideal lattice is defined over a ring learning with errors (Ring-LWE) problem. Polynomial multiplication over the ring is the most computational and time-consuming block in lattice-based cryptography. This paper presents the first hardware design of the polynomial multiplication for LAC, one of the Round-2 candidates of the NIST PQC Standardization Process, which has byte-level modulus p=251. The proposed architecture supports polynomial multiplications for different degree n (n=512/1024/2048). For designing the scheme, we used the Vivado HLS compiler, a high-level synthesis based hardware design methodology, which is able to optimize software algorithms into actual hardware products. The design of the scheme takes 274/280/291 FFs and 204/217/208 LUTs on the Xilinx Artix-7 family FPGA, requested by NIST PQC competition for hardware implementation. Multiplication core uses only 1/1/2 pieces of 18Kb BRAMs, 1/1/1 DSPs, and 90/94/95 slices on the board. Our timing result achieved in an alternative degree n with 5.052/4.3985/5.133ns.
An efficient implementation of the multiplication part is one of the significant procedures of the cryptography algorithms. In this paper, the six altered parallel multiplication methods are proposed to Implement in 192-bit for the SM2 algorithm. The CPAM, CSAM, Tri-Section Pezaris, BaughWooley array, Modified Booth, and the Montgomery multipliers are compared by considering minimum operational speed, area, and power. We used a mod m reducer circuit for comparing with similar outputs of the multiplier architectures. Through the final comparison, the Montgomery gives the efficient result by 504 LUTs, 5.532ns timing, 0.101mW dynamic power. The proposed work is implemented on the Xilinx Virtex- 7 FPGA board, and the programming language is VHDL.
An Elliptic curve is one of the significant applications of cryptography, and the 256-bit of crypto that uses a digital signature algorithm based on such a method has the same security level as 3072-bit of RSA. In other words, the elliptic curve algorithm can reach the same security level using 12 times shorter bits than the RSA method. From the computational side, an efficient and high-speed calculation methodology is required in the field of 256 bits' finite field. The most required calculation in the finite field is the addition of arithmetic. This paper discusses our latest results on 256 bits' addition arithmetic implementations, which are implemented on the Virtex6 FPGA board and Xilinx 14.5 IDE. The considered simulation results include time delay propagation, area, and power consumption.
In this paper, transition between accumulation, depletion and inversion condition of transistor with 65nm channel length as a charge controlled device is studied. As a charge controlled device, doping and acceptor concentration in the deice affect to C(V) characteristic, consequently, to transient behavior. Considerably, investigation of off-current, Short Channel Effect(SCE)s are studied. For simplicity and accuracy, quasi-static model is used to model charge distribution in junction areas within the device.
Heterojunction type solar cells are used in commercial solar energy harvesting technology. To maximize energy harvest, in other words, efficiency, designing solar cell is crucial. Therefore, studying photovoltaic(PV) effect is fundamental research in renewable energy. In some study, three-terminal heterojunction bipolar transistor solar cell is proposed for high-efficiency photovoltaic(PV) conversion [1]. To do so, we have to study the nature of semiconductor and its characteristics. Because device simulation optimization helps to maximize solar cell performance. In this paper semiconductor materials specially transistors are studied with different donor and acceptor concentration. Continuation of this study can be engaged with further investigation of designing new PV based devices, its effect, maximization in energy harvest performance.
